The present invention relates to a comparator for generating an output signal.
FIG. 1 shows a comparator, which is composed of two circuit branches that are connected to one another. The first circuit branch (designated by reference symbol SZ1 in FIG. 1) contains a first pnp-type transistor T1 and a first power source IQ1. A first voltage V1, which is one of voltages to be compared with one another, is supplied to the emitter of the transistor T1. The base and the collector of the transistor T1 are connected to ground via the power source IQ1.
The second circuit branch, which is designated by reference symbol SZ2 in FIG. 1, contains a first pnp-type transistor T2 and a first power source IQ2. A second voltage V2, which is the other of the voltages to be compared with, is applied to the emitter of the transistor T2. The collector of the transistor T2 is connected to ground via the power source IQ2, and to an output terminal O via which a signal representing the result of the comparison of the voltages VI and V2 is output. The base of the first transistor T1 and the base of the second transistor T2 are connected to one another.
A current I1, which is determined by the power source IQ1, flows through the first circuit branch SZ1. The potential which depends on the size of the voltage V1 is set at the base terminal of the transistor T1. A current I2, the size of which depends, on the difference between the voltages V1 and V2, to be more precise, on the voltage V2 and the base potential of the transistor T2 (that is dependent on the voltage V1), flows through the second circuit branch SZ2. A signal which can be tapped at the output terminal O depends on the the size of the current I2.
Such comparators are known, and further details of the same will not be described hereinafter.
The transistors T1 and T2 and the power sources IQ1 and IQ2 usually have the same dimensions. As a result, V1=V2 in the state of equilibrium (at the switch-over time) of the comparator. Otherwise, if, due to different dimensioning of the transistors and/or of the power sources, different base-emitter voltages are set at the transistors T1 and T2 in the state of equilibrium of the comparator, the applicable equation would be V1=V2xc2x1Voff in the state of equilibrium of the comparator. Voff is the known offset voltage.
The occurrence of an offset voltage is generally undesirable. At times, in particular if the comparator is to have a hysteresis, or if one of the voltages to be compared is to be a reference voltage which is not available in the configuration containing the comparator, it may be advantageous if an offset voltage is present, but such an offset voltage should be able to be set precisely and permanently to a specific value, and should preferably be variable within a relatively large range.
It would be possible to generate an offset voltage in the comparator shown in FIG. 1 by dimensioning the transistors T1 and T2 and/or the power sources IQ1 and IQ2 differently. The offset voltage Voff which is set as a result is   Voff  =            kT      q        ⁢          ln      ⁡              (                  I1          I2                )            
However, a disadvantage with this is that the offset voltage Voff is highly temperature-dependent. In addition, only small offset voltages (up to several mV) can be implemented. Otherwise, the ratio of I1 to I2 becomes too extreme.
An offset voltage generated in this way can be set neither precisely nor permanently, nor can it vary within a large range.
Another possible way of generating an offset voltage is illustrated in FIG. 2.
The configuration shown in FIG. 2 substantially corresponds to the comparator shown in FIG. 1. Elements which are designated with the same references refer to identical or corresponding elements.
However, the comparator of FIG. 2 additionally has a resistor R, which is disposed between the emitter of the second transistor T2 and the input terminal for the second voltage V2.
The offset voltage Voff, which is generated by the comparator is:
Voff=Rxc2x7I2 (for I1=I2), or   Voff  =            R      ·      I2        +                  kT        q            ⁢              ln        ⁡                  (                      I1            I2                    )                    ⁢              xe2x80x83            ⁢                        (                                    for              ⁢                              xe2x80x83                            ⁢              I1                        ≠            I2                    )                .            
A disadvantage with this is that the resistor R limits the current with which a capacitive load connected to the output terminal O can be recharged. The consequence is that the signal which is output via the output terminal O reacts relatively slowly to changes in V1 and/or V2. In other words, the comparator has a relatively slow switching behavior.
It is accordingly an object of the invention to provide a comparator configuration that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, and to provide a comparator whose offset voltage can be set precisely and permanently to a value which can vary within a large range. The offset voltage of the comparator does not lead to the other properties of the comparator to be degraded. In particular, it does not lead to a slower reaction to changes in the input voltages.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a comparator configuration containing a comparator having a first control device, a second control device, a resistor, a first power source and a second power source. The first control device has a first terminal, a second terminal, and a third terminal. The first terminal is used to input the first voltage. The second terminal is connected to the third terminal, and (via the resistor) to the terminal of the second control device. The third terminal is connected to the first power source. A current, whose size depends on the difference between the voltages applied to the first terminal and to the second terminal, flows through the third terminal.
The second control device has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal is used to input the second voltage. The second terminal is connected to the fourth terminal, and to the second terminal of the first control device via the resistor.
The third terminal is connected to the second power source. A current, whose size depends on the difference between the voltages applied to the first terminal and to the second terminal, flows via the third terminal. The output signal of the comparator is tapped at the third terminal. The fourth terminal is connected to the second terminal. A current, whose size depends on the difference between the voltages applied to the first terminal and to the second terminal, flows via the fourth terminal.
In such a comparator, a defined current flows through the resistor in the state of equilibrium (at the switch-over time) of the comparator. The voltage drop (which is caused as a result) at the resistor equals to the offset voltage of the comparator or to one of the voltage components from which the offset voltage is composed.
In accordance with another feature of the invention, the difference between the voltages applied to the first terminal and to the second terminal of the first control device and the difference between the voltages applied to the first terminal and to the second terminal of the second control device are preferably equally large. The voltage drop across the resistor is precisely the offset voltage of the comparator.
The offset voltage can be set precisely and permanently to any desired values by appropriately dimensioning the resistor and/or the power sources. Since the resistor which generates the offset voltages is not in the path, via which the output terminal of the comparator is supplied with current, generating the offset voltage does not have any influence on the speed with which the output voltage can change.
In accordance with a further feature of the invention, the first power source outputs a current, and the second power source outputs another current. The control devices and the power sources are constructed and dimensioned in such a way that the current at the fourth terminal of the second control device depends on the current of the first power source and/or another current.
In accordance with an added feature of the invention, the control devices and the power sources are constructed and dimensioned in such a way that the current at the fourth terminal of the second control device and the another current of the second power source are equally large.
In accordance with an additional feature of the invention, there is provided a third power source, which is connected to the fourth terminal of the second control device. The third power source outputs a current.
In accordance with yet another feature of the invention, the resistor receives a current. The third power source is constructed in such a way that the current of the resistor is smaller, by an amount equal to the output current of the third power source, if the third power source is provided, than if not provided.
In accordance with yet a further feature of the invention, the resistor and the currents of the power sources have magnitudes, which are variable during an operation of the comparator.
In accordance with yet an added feature of the invention, a change in the magnitudes is carried out using one of switches and control elements, which can be controlled from outside the comparator.
In accordance with yet an additional feature of the invention, the first control device includes a first transistor selected from a bipolar junction transistor and/or a field-effect transistor. The bipolar junction transistor includes an emitter, a base, and a collector. The field-effect transistor includes a source, a gate, and a drain. The first transistor having an emitter and or a source forming the first terminal of the first control device. It further includes a base or a gate, which form the second terminal of the first control device, and a collector or a drain, which form the third terminal of the first control device.
In accordance with again another feature of the invention, the second control device includes second and third transistors also selected from the bipolar junction transistor and/or the field-effect transistor. The second and third transistors having emitter or source terminals and base or gate terminals connected to one another. A common emitter or source terminal forms the first terminal of the second control device. A common base or gate terminal forms the second terminal of the second control device. A collector or drain terminal of the second transistor forms the third terminal of the second control device. A collector or drain terminal of the third transistor forms the fourth terminal of the second control device.
In accordance with again a further feature of the invention, the first, second and third transistors and the power sources are dimensioned in such a way that a same base-emitter voltage or gate-source voltage is set at the first, second and third transistors in the state of equilibrium of the comparator.
In accordance with again an added feature of the invention, the first, second and third transistors have currents flowing through them. The first, second and third transistors and the power sources are dimensioned in such a way that the currents of the first, second and third transistors are equally large in the state of equilibrium.
In accordance with again an additional feature of the invention, the power sources are dimensioned in such a way that the output current of the first power source is twice as large as the output current of the second power source, if the third power source is not provided.
In accordance with a concomitant feature of the invention, the power sources are dimensioned in such a way that the output current of the first power source is smaller, by an amount equal to the output current of the third power source, than twice the output current of the second power source, when the third power source is provided.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a comparator, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.